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preliminary xxxx-xxxxx-xe fujitsu semiconductor advance information emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90350 series mb90f352/c(s), mb90v340(s) description the mb90350-series with one full-can interface (mb90v340: 2ch) and flash rom is especially designed for automotive and industrial applications. its main feature is the on board can interface, which conforms to v2.0 part a and part b, while supporting a very exible message buffer scheme and so offering more functions than a normal full can approach. with the new 0.35 m cmos technology, fujitsu now offers on-chip flash-rom program memory up to 128 kbytes. an internal voltage booster removes the necessity for a second programming voltage. an on board voltage regulator provides 3 v to the internal mcu core. this creates a major advantage in terms of emi and power consumption. the internal pll clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 mhz clock. the unit features an 4 channel output compare unit and 6 channel input capture unit with two separate 16-bit free running timers. 2 uarts (mb90v340: 3 uarts) constitute additional functionality for communication pur- poses. packages 64-pin plastic lqfp 64-pin plastic qfp (fpt-64p-m09) (fpt-64p-m06)
mb90350 series preliminary 2 emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm features 16-bit core cpu; 4 mhz external clock (24 mhz internal, 42 ns instr. cycle time) new 0.35 m cmos process technology internal voltage regulator supports 3 v mcu core, offering low emi and low power consumption ?ures one full-can interface (mb90v340: 2ch); conforming to version 2.0 part a and part b, ?xible message buffering (mailbox and fifo buffering can be mixed) powerful interrupt functions (8 progr. priority levels; 8 external interrupts) ei2os - automatic transfer function indep.of cpu; 16 ch. of intelligent i/o services dma 18-bit time-base counter watchdog timer 2 full duplex uarts (sci/lin) (mb90v340: 3 uarts) one ch i 2 c with 400 kbit/s (devices with c-suf?) a/d converter : 15 ch. analog inputs (resolution 10 bits or 8 bit, conversion time 3 s) 16-bit reload timer 4 ch icu (input capture) 16 bit x6 ch ocu (output compare) 16 bit 4 ch 16-bit free running timer 2 ch (frt0 : icu 0/1, frt1 : icu 4/5/6/7, ocu 4/5/6/7) 8/16-bit programmable pulse generator 6ch 16-bit / 10ch 8-bit (mb90v340: 8ch 16bit / 12ch 8bit) optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) 4-byte instruction execution queue signed multiply (16 bit 16 bit) and divide (32 bit/16 bit) instructions available program patch function fast interrupt processing low power consumption - 10 different power saving modes : (sleep, stop, cpu intermittent mode, ...) 32 khz subsytem clock (devices without s-suf?) external bus interface programmable input levels (automotive / cmos-schmitt (initial level is automotive), for external bus also ttl level) packages : 64-pin plastic qfp, 64-pin plastic lqfp controller area network (can) - license of robert bosch gmbh
mb90350 series preliminary emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 3 product lineup (continued) part number parameter mb90f352/c(s) mb90v340(s) cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier ( 1, 2, 3, 4, x6, x8 ,1/2 when pll stops) minimum instruction execution time : 42 ns (4 mhz osc. pll 6) rom boot-block, flash memory 128 kbytes external ram 4 kbytes 30 kbytes emulator-specific power supply *1 ? none technology 0.35 m cmos with on-chip voltage regulator for internal power supply + flash memory with on-chip charge pump for programming voltage 0.35 m cmos with on-chip voltage regulator for internal power supply operating voltage range 3.5 - 5.5 v (4.5 - 5.5 v if a/d converter is used) 5 v 10 % temperature range ? 40 c to 105 c ? package qfp-64, lqfp-64 pga-299 uart 2 channels 3 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbit/s) devices with ??suffix: 1 channel devices without ??suffix: ? 2 channels a/d converter 15 channels 15 channels 10-bit or 8-bit resolution conversion time : min 3 s include sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = system clock frequency) supports external event count function for 2 channels (ch.1 and ch.3) 16-bit i/o timer (2 channels) signals an interrupt when overflowing operation clock freq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys = system clock freq.) i/o timer 0 (clock input frck0) corresponds to icu 0/1 i/o timer 1 (clock input frck1) corresponds to icu 4/5/6/7, ocu 4/5/6/7 both i/o timers support timer clear when a match with output compare (channel 4) i/o timer 1 supports timer clear when a match with out- put compare (channel 4) 16-bit output compare (4 channels) signals an interrupt when a match with 16-bit i/o timer. 16-bit compare registers. four compare registers can be used to generate three pwm output signals. 16-bit input capture (6 channels) rising edge, falling edge or rising & falling edge sensitive signals an interrupt upon external event
mb90350 series preliminary 4 emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm *1 : it is setting of jumper switch si when emulation pod (mb2147) is used. please refer to the emulator hardware manual about details. *2 : embedded algorithm is a trade mark of advanced micro devices inc. part number parameter mb90f352/c(s) mb90v340(s) 8/16-bit programmable pulse generator 10 ch (8 bit) / 6 ch (16 bit) 12 8-bit reload counters 12 ch (8 bit) / 8 ch (16 bit) 16 8-bit reload counters supports 8-bit and 16-bit operation modes a pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter operation clock freq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 102.4 s@fosc = 5 mhz (fsys = system clock frequency, fosc = oscillation clock frequency) can interface 1 channel 2 channels conforms to can specification version 2.0 part a and b automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and id? supports multiple messages flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps external interrupt (8 channels) can be programmed edge sensitive or level sensitive 32 khz subclock for low power operation devices without ??suffix: yes devices with ??suffix: ? i/o ports virtually all external pins can be used as general purpose i/o all push-pull outputs bit-wise programmable as input/output or peripheral signal programmable in groups of 8 as cmos schmitt trigger/ automotive inputs (default) ttl input level programmable for external bus (default for external reset vector fetch) flash memory supports automatic programming, embedded algorith- m tm*2 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles : 10,000 times data retention time : 10 years boot block configuration erase can be performed on each block block protection with external programming voltage ?
mb90350 series preliminary emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 5 pin assignments mb90v340(s) as seen with probe cable for lqfp-64 (top view) ( fpt-64p-m09) *) mb90v340: x0a, x1a mb90v340s: p40, p41 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 avcc p63/an3/ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2(3) p60/an0/ppg0(1) p37/clk/out7 p36/rdy/out6 p34/hrq/out4 p33/wrhx/tx2 p32/wrlx/wrx/rx2/int10r p31/rdx/in5 p30/ale/in4 p25/a21/in1 c vcc p35/hakx/out5 10 11 12 13 14 15 16 1234567 9 8 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 p04/ad04/int12 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 md0 md1 md2 vss p41/x1a *) p40/x0a *) p45/scl0/frck1 vss x1 x0 rstx p24/a20/in0 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15/sck4 p16/ad14/sot4 p15/ad13/sin4 p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 avss avrh p64/an4/ppg8(9) p65/an5/ppga(b) p66/an6/ppgc(d) p67/an7/ppge(f) p50/an8/sin2 p51/an9/sot2 p52/an10/sck2 p53/an11/tin3 p44/sda0/frck0 p43/in7/tx1 p42/in6/rx1/int9r p56/an14 p55/an13 p54/an12/tot3 lqfp - 64
mb90350 series preliminary 6 emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm mb90f352(s) (top view) (fpt-64p-m09) *) mb90f352: x0a, x1a mb90f352s: p40, p41 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 avcc p61/an1 p60/an0 p37/clk/out7 p36/rdy/out6 p35/hakx/out5 p34/hrq/out4 p32/wrlx/wrx/int10r p31/rdx/in5 p30/ale/in4 p45/scl0/frck1 p44/sda0/frck0 p25/a21/in1 c vcc p33/wrhx 10 11 12 13 14 15 16 1234567 9 8 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 p04/ad04/int12 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 md0 md1 md2 p41/x1a *) p40/x0a *) vss p43/in7/tx1 vss x0 x1 rstx p24/a20/in0 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 avss avrh p64/an4/ppg8(9) p65/an5/ppga(b) p66/an6/ppgc(d) p67/an7/ppge(f) p50/an8/sin2 p51/an9/sot2 p52/an10/sck2 p53/an11/tin3 p56/an14 p55/an13 p54/an12/tot3 lqfp - 64 p62/an2/ppg4(5) p63/an3/ppg6(7) p42/in6/rx1/iint9r
mb90350 series preliminary emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 7 mb90f352(s) (top view) (fpt-64p-m06) *) mb90f352: x0a, x1a mb90f352s: p40, p41 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 avcc p61/an1 p60/an0 p37/clk/out7 p36/rdy/out6 p35/hakx/out5 p34/hrq/out4 p32/wrlx/wrx/int10r p31/rdx/in5 p30/ale/in4 p45/scl0/frck1 p44/sda0/frck0 p25/a21/in1 c vcc p33/wrhx 10 11 12 13 14 15 16 1234567 9 8 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 p04/ad04/int12 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 md0 md1 md2 p41/x1a *) p40/x0a *) vss p43/in7/tx1 vss x0 x1 rstx p24/a20/in0 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 avss avrh p64/an4/ppg8(9) p65/an5/ppga(b) p66/an6/ppgc(d) p67/an7/ppge(f) p50/an8/sin2 p51/an9/sot2 p52/an10/sck2 p53/an11/tin3 p56/an14 p55/an13 p54/an12/tot3 qfp - 64 p62/an2/ppg4(5) p63/an3/ppg6(7) p42/in6/rx1/iint9r
mb90350 series preliminary 8 emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm pin description pin no. pin name circuit type function fpt-64p-m06 fpt-64p-m09 46 45 rstx e reset input 48 47 x0 a oscillation input 47 46 x1 oscillation output 25 to 31 24 to 31 p00 to p07 g general purpose io ad00 to ad07 i/o pins for 8 lower bits of the external address/data bus. this function is enabled when the external bus is enabled. int8 to int15 external interrupt request input pins for int8 to int15. 33 32 p10 g general purpose io ad08 i/o pin for 8th bit of the external address/data bus. this function is enabled when the external bus is enabled. tin1 event input pin for the reload timers 1. 34 33 p11 g general purpose io ad09 i/o pin for 9th bit of the external address/data bus. this function is enabled when the external bus is enabled. tot1 output pin for the reload timer 1. 35 34 p12 g general purpose io ad10 i/o pin for 10th bit of the external address/data bus. this function is enabled when the external bus is enabled. sin3 serial data input pin for uart3. int11r second external interrupt request input pin for int11. 36 35 p13 g general purpose io ad11 i/o pin for 11th bit of the external address/data bus. this function is enabled when the external bus is enabled. sot3 serial data output pin for uart3. 37 36 p14 g general purpose io ad12 i/o pin for 12th bit of the external address/data bus. this function is enabled when the external bus is enabled. sck3 clock i/o pin for uart3. 38 37 p15 g general purpose io ad13 i/o pin for 13th bit of the external address/data bus. this function is enabled when the external bus is enabled. sin4 serial data input pin for uart4 (mb90v340 only). 39 38 p16 g general purpose io ad14 i/o pin for 14th bit of the external address/data bus. this function is enabled when the external bus is enabled. sot4 serial data output pin for uart4 (mb90v340 only).
mb90350 series preliminary emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 9 40 39 p17 g general purpose io ad15 i/o pin for 15th bit of the external address/data bus. this function is enabled when the external bus is enabled. sck4 clock i/o pin for uart4 (mb90v340 only). 41 to 44 40 to 43 p20 to p23 g general purpose io a16 to a19 output pins for a16 to a17 of the external address bus. this function is enabled when the external bus is enabled. ppg9,ppgb, ppgd,ppgf output pins for ppgs. 45 44 p24 g general purpose io a20 output pin for a20 of the external address bus. this func- tion is enabled when the external bus is enabled. in0 data sample input pins for input capture icu0. 52 51 p25 g general purpose io a21 output pin for a21 of the external address bus. this func- tion is enabled when the external bus is enabled. in1 data sample input pin for input capture icu1. 55 54 p30 g general purpose io ale address latch enable output pin. this function is enabled when the external bus is enabled. in4 data sample input pin for input capture icu4. 56 55 p31 g general purpose io rdx read strobe output pin for the data bus. this function is enabled when the external bus is enabled. in5 data sample input pin for input capture icu5. 57 56 p32 g general purpose io wrlx / wrx write strobe output pin for the data bus. this function is enabled when both the external bus and the wr/wrl pin output are enabled. wrl is used to write-strobe 8 lower bits of the data bus in 16-bit access while wr is used to write-strobe 8 bits of the data bus in 8-bit access. rx2 rx input pin for can2 interface (mb90v340 only). int10r second external interrupt request input pin for int10. pin description (continued) pin no. pin name circuit type function fpt-64p-m06 fpt-64p-m09
mb90350 series preliminary 10 emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 58 57 p33 g general purpose io wrhx write strobe output pin for the 8 higher bits of the data bus. this function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the wrh output pin is enabled. tx2 tx output pin for can2 (mb90v340 only). 59 58 p34 g general purpose io hrq hold request input pin. this function is enabled when both the external bus and the hold function are enabled. out4 waveform output pin for output compares ocu4. 60 59 p35 g general purpose io hakx hold acknowledge output pin. this function is enabled when both the external bus and the hold function are enabled. out5 waveform output pin for output compares ocu5. 61 60 p36 g general purpose io rdy ready input pin. this function is enabled when both the external bus and the external ready function are enabled. out6 waveform output pin for output compares ocu6. 62 61 p37 g general purpose io clk clk output pin. this function is enabled when both the external bus and clk output are enabled. out7 waveform output pin for output compares ocu7. 63 to 64 62 to 63 p60 to p61 i general purpose io an0 to an1 analog input pins for the a/d converter. ppg0,2 output pins for ppgs (mb90v340 only). 4 to 9 3 to 8 p62 to p67 i general purpose io an2 to an7 analog input pins for the a/d converter. ppg4,6,8 ppga,c,e output pins for ppgs. 10 9 p50 i general purpose io an8 analog input pin for the a/d converter sin2 serial data input pin for uart2. 11 10 p51 i general purpose io an9 analog input pin for the a/d converter sot2 serial data output pin for uart2. pin description (continued) pin no. pin name circuit type function fpt-64p-m06 fpt-64p-m09
mb90350 series preliminary emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 11 12 11 p52 i general purpose io an10 analog input pin for the a/d converter sck2 clock i/o pin for uart2. 13 12 p53 i general purpose io an11 analog input pin for the a/d converter tin3 event input pin for the reload timer 3. 14 13 p54 i general purpose io an12 analog input pin for the a/d converter tot3 output pin for the reload timer 3. 15 to 16 14 to 15 p55 to p56 i general purpose io an13 to an14 analog input pins for the a/d converter 17 16 p42 f general purpose io in6 data sample input pin for input capture icu6. rx1 rx input pin for can1 interface. int9r second external interrupt request input pin for int10. 18 17 p43 f general purpose io in7 data sample input pin for input capture icu7. tx1 tx output pin for can1. 53 52 p44 h general purpose io sda0 serial data i/o pin for i2c 0 (only devices with c-suf?) frck0 input for the 16-bit io timer 0 54 53 p45 h general purpose io scl0 serial clock i/o pin for i2c 0 (only devices with c-suf?) frck1 input for the 16-bit io timer 1 20 to 21 19 to 20 p40 to p41 f general purpose io (only for devices with s-suf?) x0a , x1a b oscillator input pins for sub-clock (only for devices without s-suf?) 22 21 md2 d input pin for specifying the operating mode. the pins must be directly connected to vcc or vss 23 to 24 22 to 23 md1 to md0 c input pins for specifying the operating mode. the pins must be directly connected to vcc or vss 19 49 18 48 vss power (0v) input pins 50 49 vcc power (3.5v to 5.5v) input pin pin description (continued) pin no. pin name circuit type function fpt-64p-m06 fpt-64p-m09
mb90350 series preliminary 12 emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 51 50 c k this is the power supply stabilization capacitor pin. it should be connected to a higher than or equal to 0.1 f ceramic capacitor. 1 64 avcc k vcc power input pin for analog circuits 21 avss k vss power input pin for analog circuits and lower refer- ence voltage input for the a/d converter 32 avrh l reference voltage input for the a/d converter. this power supply must be turned on or off while a voltage higher than or equal to avrh is applied to avcc . pin description (continued) pin no. pin name circuit type function fpt-64p-m06 fpt-64p-m09
mb90350 series preliminary emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 13 i/o circuit type type circuit remarks a oscillation circuit high-speed oscillation feedback resistor = approx. 1 m ? b oscillation circuit low-speed oscillation feedback resistor = approx. 1 m ? c mask rom and eva device: cmos hysteresis input pin resistor value : approx. 50 k ? (typ) flash device: cmos input pin resistor value : approx. 50 k ? (typ) d mask rom and eva device: cmos hysteresis input pin resistor value : approx. 50 k ? (typ) pull-down resistor valule: approx. 50 k ? flash device: cmos input pin resistor value : approx. 50 k ? (typ) no pull-down e cmos hysteresis input pin resistor value : approx. 50 k ? (typ) pull-up resistor valule: approx. 50 k ? x 1 x 0 xout standby control signal x1a x0a xout standby control signal r hysteresis inputs r pull-down resistor hysteresis inputs r pull-up resistor hysteresis inputs
mb90350 series preliminary 14 emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm f cmos level output(i ol = 4 ma) cmos hysteresis inputs (with the standby-time input shutdown function) automotive input (with the standby- time input shutdown function) g cmos level output(i ol = 4 ma) cmos hysteresis inputs (with the standby-time input shutdown function) automotive input (with the standby- time input shutdown function) ttl input (with the standby-time input shutdown function) programmalble pullup resistor: 50k ? approx. h cmos level output(i ol = 3 ma) cmos hysteresis inputs (with the standby-time input shutdown function) automotive input (with the standby- time input shutdown function) (continued) type circuit remarks pout nout r hysteresis inputs automotive inputs standby control for input shutdown hysteresis inputs automotive inputs ttl inputs pout nout r standby control for input shutdown control for pull-up pout nout r hysteresis inputs automotive inputs standby control for input shutdown
mb90350 series preliminary emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 15 i cmos level output(i ol = 4 ma) cmos hysteresis inputs (with the standby-time input shutdown function) automotive input (with the standby- time input shutdown function) a/d analog input k power supply input protection circuit l a/d converter ref+ (avrh) power supply input pin, with the protection circuit flash devices do not have a protection circuit against vcc for pin avrh (continued) type circuit remarks pout nout r hysteresis inputs automotive inputs standby control for input shutdown analog input in ane avr ane
mb90350 series preliminary 16 emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm handling devices special care is required for the following when handling the device : preventing latch-up treatment of unused pins using external clock power supply pins (v cc /v ss ) pull-up/down resistors crystal oscillator circuit turning-on sequence of power supply to a/d converter and analog inputs connection of unused pins of a/d converter notes on energization initialization 1. preventing latch-up cmos ic chips may suffer latch - up under the following conditions : a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the rated voltage is applied between v cc and v ss . the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current drastically, causing thermal damage to the device. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage. 2. handling unused pins leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. therefore they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k ? . unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 3. using external clock to use external clock, drive the x0 pin and leave x1 pin open. 4. power supply pins (v cc /v ss ) if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. to reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. connect v cc and v ss to the device from the current supply source at a low impedance. x0 x1 mb90350 series
mb90350 series preliminary emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 17 as a measure against power supply noise, connect a capacitor of about 0.1 f as a bypass capacitor between v cc and v ss in the vicinity of v cc and v ss pins of the device 5. pull-up/down resistors the mb90340 series does not support internal pull-up/down resistors (except port0 - port3: programmable pull- up resistors). use external components where needed. 6. crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with a ground area for stabilizing the operation. 7. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh) and analog inputs (an0 to an11) after turning-on the digital power supply (v cc ) . turn-off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that the voltage not exceed avrh or av cc (turning on/off the analog and digital power supplies simultaneously is acceptable) . 8. connection of pins of a/d converter if a/d converter is not used connect pins of unused a/d converter to av cc = v cc , av ss = avrh = v ss . 9. notes on energization to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more s (0.2 v to 2.7 v) 10. initialization in the device, there are internal registers which is initialized only by a power-on reset. to initialize these registers, turn on the power again. vcc vss vss vcc vss vcc mb90350 series vcc vss vcc vss
mb90350 series preliminary 18 emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm block diagrams mb90v340(s) *1) only for mb90v340 ram 30k uart prescaler 10-bit adc 15ch 16-bit reload timer 4ch io timer 0 clock controller input capture 8ch output compare 4ch can controller external interrupt 16lx cpu fmc-16 bus x0,x1 rst sot4 to sot2 sck4 to sck2 sin4 to sin2 avcc avss an14 to an0 avrh tin3, tin1 tot3, tot1 in7 to in4, out7 to out4 rx2 to rx1 tx2 to tx1 int15 to int8 external bus interface ad15 to ad00 a21 to a16 ale rd wrl wrh hrq hak rdy clk x0a,x1a *1 3ch io timer 1 frck0 frck1 8/16-bit ppg 12/8ch ppg6, ppg4, i 2 c interface sda0 scl0 2ch 3ch 1ch ppg2, ppg0 ppgf to ppg8, 8ch in1 to in0
mb90350 series preliminary emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm 19 mb90f352/c(s) *1) only for devices without ??suf? *2) only for devices with ??suf? ram 4k rom/flash uart prescaler 10-bit adc 15ch 16-bit reload timer 4ch io timer 0 clock controller input capture 6ch output compare 4ch can controller 16lx cpu fmc-16 bus x0,x1 rst sot3 to sot2 sck3 to sck2 sin3 to sin2 avcc avss an14 to an0 avrh tin3, tin1 tot3, tot1 in7 to in4, out7 to out4 rx1 tx1 external bus interface ad15 to ad00 a21 to a16 ale rd wrl wrh hrq hak rdy clk x0a,x1a *1 128k 2ch io timer 1 frck0 frck1 8/16-bit ppg 10/6ch ppgf to ppg8, 1ch 2ch 8ch external interrupt int15 to int8 ppg6, ppg4 in1 to in0 i 2 c interface sda0 *2 scl0 *2 1ch
mb90350 series preliminary 20 emdc-ws 31/march/2003 /usr/projects/mb90350/doc/datasheet/ds/mb90350_info_0.8.fm memory space note : the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits are the same, the table in rom can be referenced without using the far speci cation in the pointer declaration. for example, an attempt to access 00c000 h accesses the value at ffc000 h in rom. the rom area in bank ff exceeds 32 kbytes, and its entire image cannot be shown in bank 00. the image between ff8000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff7fff h is visible only in bank ff. ffffffh ff0000h feffffh fe0000h fdffffh fd0000h fcffffh fc0000h 008000h 0078ffh 000100h 0000efh 000000h mb90v340(s) rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) peripheral ram 30k peripheral rom (fb bank) fbffffh fb0000h faffffh fa0000h f9ffffh f90000h rom (f9 bank) rom (fa bank) 00ffffh rom (image of ff bank) 007fffh 007900h 007fffh mb90f352/c/s/cs ffffffh ff0000h feffffh fe0000h 0010ffh 000100h 0000efh 000000h rom (ff bank) rom (fe bank) ram 4k peripheral 007900h peripheral rom (image of ff bank) 008000h c00100h fdffffh external bus external bus 00ffffh

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